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? 2009 semtech corporation power management 1 SC653 light management unit with 2 ldos and sempulse ? interface features input supply voltage range 2.9v to 5.5v four programmable current sinks with 29 steps from 0ma to 25ma very high e ciency charge pump driver system with three modes 1x, 1.5x and 2x two programmable 200ma low-noise ldo regulators charge pump frequency 250khz sempulse single wire interface backlight current accuracy 1.5% typical backlight current matching 0.5% typical fade-in/fade-out feature for main backlight automatic sleep mode (leds o ) i q = 100a shutdown current 0.1a (typical) ultra-thin package 2.3 x 2.3 x 0.6 (mm) lead-free and halogen-free weee and rohs compliant applications cellular phones, smart phones, and pdas lcd modules portable media players digital cameras and gps units display backlighting and led indicators ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC653 is a highly integrated light management unit that provides two low-noise ldos, a multi-mode high efficiency charge pump, and four programmable led drivers. performance is optimized for use in single-cell li- ion battery applications. the load and supply conditions determine whether the charge pump operates in 1x, 1.5x, or 2x mode. a program- mable fading feature can be enabled to gradually adjust the backlight current, simplifying control software. the low-dropout, low-noise linear regulators can be used for powering a camera module or other peripheral circuits. the SC653 uses the proprietary sempulse ? single wire interface. this interface controls all functions of the device, including backlight currents and ldo voltage outputs. the single wire interface minimizes microcontroller and interface pin counts. the SC653 enters sleep mode when all the led drivers are disabled. in this mode, the quiescent current is reduced while the device continues to monitor the sempulse inter- face. the two ldos can be enabled when the device is in sleep mode. SC653 in spif byp gnd1 gnd2 out bl1 c in 2.2 f main backlight ldo1 c1+ sempulse interface v ldo1 = 1.5v to 3.3v v ldo2 = 1.2v to 1.8v c out 2.2 f c ldo2 1 f c ldo1 1 f c2 2.2 f c1 2.2 f ldo2 bl2 bl3 bl4 c2+ c1- c2- enl1 enl2 v bat = 2.9v to 5.5v gnd1 gnd2 gnd1 c byp 22nf gnd1 gnd2 gnd2 gnd2 us patents: 6,504,422; 6,794,926 typical application circuit october 21, 2009
SC653 2 pin con guration marking information ordering information device package SC653ultrt (1)(2) mlpq-ut-18 2.32.3 SC653evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free packaging only. device is weee and rohs compliant, and halogen-free. top view 1 2 3 4 t byp bl3 bl1 bl2 56 7 89 enl1 c1+ c2- c1- c2+ 13 12 11 10 14 15 16 17 18 enl2 gnd1 spif bl4 out ldo1 ldo2 in gnd2 653 yyww xxxx mlpq-ut-18; 2.3x2.3, 18 lead ja = 45c/w yyww = date code xxxx = semtech lot number
SC653 3 exceeding the above speci cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) v f(max) = 1.0v when v in = 2.9v, higher v in supports higher v f(max) (3) calculated from package in still air, mounted to 3 x 4.5, 4 layer fr4 pcb with thermal vias under the exposed pad per jes d51 standards. absolute maximum ratings in, out (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 c1+, c2+ (v) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v out + 0.3) pin voltage all other pins (v) . . . . . . . . . -0.3 to (v in + 0.3) out short circuit duration . . . . . . . . . . . . . . con tinuous ldo1, ldo2 short circuit duration . . . . . . con tinuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 recommended operating conditions ambient temperature range (c) . . . . . . . . -40 t a +85 input voltage (v) . . . . . . . . . . . . . . . . . . . . . . . 2.9 v in 5.5 output voltage (v) . . . . . . . . . . . . . . . . . . . . . 2.5 v out 5.25 voltage di erence between any two leds (v). . v f < 1.0 (2) thermal information thermal resistance, junction to ambient (3) (c/w) . . . . . . . 45 maximum junction temperature (c) . . . . . . . . . . . . . . . +150 storage temperature range (c) . . . . . . . . . . . . -65 to +150 peak ir reflow temperature (10s to 30s) (c) . . . . . . . +260 unless otherwise noted, t a = +25c for typ, -40oc to +85c for min and max, t j(max) = 125oc, v in = 3.7v, c in = c 1 = c 2 = 2.2f, c out = 2.2f (esr = 0.03), v f 1.0v (1) parameter symbol conditions min typ max units supply speci cations shutdown current i q(off) shutdown 0.1 2 a total quiescent current i q sleep (ldos o ), spif = v in (2) 100 a sleep (ldos on), spif = v in (2) , i ldon = 0ma 220 charge pump in 1x mode, i out = 20ma, i bln = 5ma 3.8 ma charge pump in 1.5x mode, i out = 20ma, i bln = 5ma 4.6 charge pump in 2x mode, i out = 20ma, i bln = 5ma 4.6 charge pump electrical speci cations maximum total output current i out(max) v in > 3.2v, sum of all active led currents, v out(max) = 4.2v 100 ma backlight current setting i bl nominal setting for bl1 thru bl4 0.5 25 ma backlight current accuracy i bl_acc i bln = 12ma (3) , t a = 25c -8 1.5 +8 % backlight current matching i bl-bl i bln = 12ma (4) -3.5 0.5 +3.5 % electrical characteristics
SC653 4 parameter symbol conditions min typ max units charge pump electrical speci cations (continued) 1x mode to 1.5x mode falling transition voltage v trans1x i out = 40ma, i bln = 10ma, v out = 3.2v 3.27 v 1.5x mode to 1x mode hysteresis v hyst1x i out = 40ma, i bln = 10ma, v out = 3.2v 250 mv 1.5x mode to 2x mode falling transition voltage v trans1.5x i out = 40ma, i bln = 10ma, v out = 4.0v (5) 2.92 v 2x mode to 1.5x mode hysteresis v hyst1.5x i out = 40ma, i bln = 10ma, v out = 4.0v (5) 300 mv current sink o -state leakage current i bln v in = v bln = 4.2v 0.1 1 a pump frequency f pump v in = 3.2v 250 khz ldo electrical speci cations ldo1 voltage setting v ldo1 range of nominal settings in 100mv increments 1.5 3.3 v ldo2 voltage setting v ldo2 range of nominal settings in 100mv increments 1.2 1.8 v ldo1, ldo2 output voltage accuracy v ldo i ldon = 1ma, t a = 25c, 2.9v v in 4.2v -3 +3 % i ldon = 1ma to 100ma, 2.9v v in 4.2v -3.5 3 +3.5 % line regulation v line i ldo1 = 1ma, v out = 2.8v 2.1 7.2 mv i ldo2 = 1ma, v out = 1.8v 1.3 4.8 load regulation v load v ldo1 = 3.3v, i ldo1 = 1ma to 100 ma 25 mv v ldo2 = 1.8v, i ldo2 = 1ma to 100 ma 20 dropout voltage (6) v d i ldo1 = 150ma 150 200 mv power supply rejection ratio psrr ldo1 1.5v < v ldo1 < 3.0v, f < 1khz, c byp = 22nf, i ldo1 = 50ma with 0.5v p-p supply ripple 55 db psrr ldo2 1.2v < v ldo2 , f < 1khz, c byp = 22nf, i ldo2 = 50ma, with 0.5v p-p supply ripple 60 output voltage noise e n-ldo1 ldo1, 10hz < f < 100khz, c byp = 22nf, c ldon = 1f, i ldo1 = 50 ma, 1.5v < v ldo1 < 3.0v 100 v rms e n-ldo2 ldo2, 10hz < f < 100khz, c byp = 22nf, c ldo = 1f, i ldo2 = 50 ma 50 minimum output capacitor c ldo(min) 1f electrical characteristics (continued)
SC653 5 electrical characteristics (continued) parameter symbol conditions min typ max units digital i/o electrical speci cations (spif, enl1, enl2) input high threshold (7) v ih v in = 5.5v 1.6 v input low threshold (7) v il v in = 3.0v 0.4 v input high current i ih v in = 5.5v -1 +1 a input low current i il v in = 5.5v -1 +1 a sempulse electrical speci cations (spif) sempulse start-up time (8) t su 1ms bit pulse duration (7) t hi 0.75 250 s duration between bits (7) t lo 0.75 250 s hold time - address (7) t holda spif is held high 500 5000 s hold time - data (7) t holdd spif is held high 500 s bus reset time (7) t br spif is held high 10 ms shutdown time (9) t sd spif is pulled low 10 ms fault protection output short circuit current limit i out(sc) out pin shorted to gnd 250 ma ldo current limit i lim v ldon enabled 200 ma over-temperature t otp rising threshold 165 c t hys hysteresis 30 c charge pump over-voltage protection v ovp out pin open circuit, v out = v ovp rising threshold 5.3 5.7 6.0 v under voltage lockout v uvlo-off increasing v in 2.7 v v uvlo-hys hysteresis 800 mv notes: (1) v f is the voltage difference between any two leds. (2) spif is high for more than 10ms (3) subscript n = 1 and 2 for the ldos, and n = 1, 2, 3, and 4 for the backlights. (4) current matching equals [i bl(max) - i bl(min ] / [i bl(max) + i bl(min) ]. (5) test voltage is v out = 4.0v a relatively extreme led voltage to force a transition during test. typically v out = 3.2v for white leds. (6) dropout is de ned as (v in - v ldo1 ) when v ldo1 drops 100mv from nominal. dropout does not apply to ldo2 since it has a maximum output voltage of 1.8v. (7) the source driver used to provide the sempulse output must meet these limits. (8) the sempulse start-up time is the minimum time that the spif pin must be held high to enable the part before starting communication. (9) the sempulse shutdown time is the minimum time that the spif pin must be pulled low to shut the part down.
SC653 6 typical characteristics battery current (4 leds) 25ma each 80 100 120 140 160 180 2.7 3 3.3 3.6 3.9 4.2 v in (v) battery current (ma) v out = 3.56v, i out = 100ma, 25c backlight e ciency (4 leds) 12ma each backlight e ciency ( 4 leds) 5.0ma each battery current ( 4 leds) 5.0ma each battery current (4 leds) 12ma each backlight e ciency (4 leds) 25ma each 40 50 60 70 80 90 2.7 3 3.3 3.6 3.9 4.2 v in (v) battery current (ma) v out = 3.41v, i out = 48ma, 25c 0 10 20 30 40 50 2.7 3 3.3 3.6 3.9 4.2 v in (v) battery current (ma) v out = 3.27v, i out = 20ma, 25c 50 60 70 80 90 100 2.7 3 3.3 3.6 3.9 4.2 v in (v) efficiency (%) v out = 3.56v, i out = 100ma, 25c 50 60 70 80 90 100 2.7 3 3.3 3.6 3.9 4.2 v in (v) efficiency (%) v out = 3.41v, i out = 48ma, 25c 50 60 70 80 90 100 2.7 3 3.3 3.6 3.9 4.2 v in (v) efficiency (%) v out = 3.27v, i out = 20ma, 25c
SC653 7 typical characteristics (continued) psrr vs. frequency 1.8v -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) psrr (db) v in = 3.7v, i out = 50ma, t a = 25 c line regulation (ldo2) i ldo1 = 1ma, v ldo1 = 1.2v and 1.8v, 25c -1.5 -1 -0.5 0 0.5 1 1.5 2.7 3 3.3 3.6 3.9 4.2 v in (v) output voltage variation (mv) 1.8v 1.2v psrr vs. frequency 2.8v line regulation (ldo1) ldo noise vs. load current 1.8v 0 20 40 60 80 100 020406080 100 i out (ma) v ldo =1.8v, v in =3.7v, 25c, 10hz < f < 100khz noise ( v rms ) ldo noise vs. load current 2.8v 0 20 40 60 80 100 0 30 60 90 120 150 i out (ma) v ldo =2.8v, v in =3.7v, 25c, 10hz < f < 100khz noise ( v rms ) v in = 3.7v, i out = 50ma, t a = 25c -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 frequency (hz) psrr (db) -3 -2 -1 0 1 2 3 2.7 3 3.3 3.6 3.9 4.2 v in (v) output voltage variation (mv) i ldo1 = 1ma, v ldo1 = 2.8v, 25c 2.8v
SC653 8 typical characteristics (continued) load regulation (ldo1) load regulation (ldo2) -30 -25 -20 -15 -10 -5 0 0 40 80 120 160 200 i ldo (ma) output voltage variation (mv) v in = 3.7v, 25c 1.2v 1.5v 1.8v output short circuit current limit time (1ms/div) v out (1v/div) i out (200ma/div) v out =0v, v in =4.2v, 25c ldo load transient response (3.3v) time (20 s/div) v ldo (50mv/div) i ldo (100ma/div) v in =3.7v, v ldo =3.3v, i ldo =1 to 100ma, 25c ldo load transient response (1.2v) time (20 s/div) v ldo (50mv/div) i ldo (100ma/div) v in =3.7v, v ldo =1.2v, i ldo =1 to 100ma, 25c ldo load transient response (1.8v) time (20 s/div) v ldo (50mv/div) i ldo (100ma/div) v in =3.7v, v ldo =1.8v, i ldo =1 to 100ma, 25c -35 -30 -25 -20 -15 -10 -5 0 0 40 80 120 160 200 i ldo (ma) output voltage variation (mv) v in =3.7v, 25c 1.5v 1.8v 2.5v 2.8v 3.3v
SC653 9 typical characteristics (continued) ripple 1x mode v in (100mv/div) v out (100mv/div) i bl (20ma/div) v in =3.7v, 4 backlights 25 ma each, 25c time (20 s/div) ripple 1.5x mode v in (100mv/div) v out (100mv/div) i bl (20ma/div) v in =2.9v, 4 backlights 25 ma each, 25c time (20 s/div) output open circuit protection time (200 s/div) v bl (500mv/div) v out (1v/div) i bl (20ma/div ) v in =3.7v, 25c ripple 2x mode v in (100mv/div) v out (100mv/div) i bl (20ma/div) v in =2.9v, 4 backlights 25 ma each, 25c time (20 s/div) 5.42v
SC653 10 pin descriptions pin # pin name pin function 1 byp bypass pin for voltage reference ground c byp to gnd1 on ground island. 2 bl1 current sink output for main backlight led 1 leave this pin open if unused 3 bl2 current sink output for main backlight led 2 leave this pin open if unused 4 bl3 current sink output for main backlight led 3 leave this pin open if unused 5 bl4 current sink output for main backlight led 4 leave this pin open if unused 6 spif sempulse single wire interface pin used to enable/disable the device and to con gure all regis- ters (refer to register map and sempulse interface sections) 7 gnd1 ground pin ground c byp , c ldo1 , c ldo2 to gnd1 on ground island. 8 enl1 (1) ldo1 enable input active high 9 enl2 (2) ldo2 enable input active high 10 c2- negative connection to bucket capacitor 2 11 c1- negative connection to bucket capacitor 1 12 c1+ positive connection to bucket capacitor 1 13 c2+ positive connection to bucket capacitor 2 14 out charge pump output all led anode pins should be connected to this pin 15 in battery voltage input 16 gnd2 ground pin connect to ground plane 17 ldo1 output of ldo1 ground c ldo1 to gnd1 on ground island. 18 ldo2 output of ldo2 ground c ldo2 to gnd1 on ground island. t thermal pad thermal pad for heatsinking purposes connect to ground plane using multiple vias. this pad is internally connected to ground and to pins 7 and 16. notes: (1) enl1 must be high for the spif interface to control ldo1. when low, enl1 disables ldo1. (2) enl2 must be high for the spif interface to control ldo2. when low, enl2 disables ldo2.
SC653 11 block diagram oscillator current setting dac sempulse tm digital interface and logic control fractional charge pump (1x, 1.5x, 2x) voltage setting dac ldo1 ldo2 v in 2 3 4 5 17 18 16 9 8 12 6 11 13 c1+ c1- c2+ c2- out 14 bl1 bl2 bl3 bl4 in spif enl2 ldo2 ldo1 gnd2 bandgap reference 1 byp 15 enl1 10 v in v in 7 gnd1
SC653 12 general description this design is optimized for handheld applications sup- plied from a single li-ion cell and includes the following key features: a high e ciency fractional charge pump that supplies power to all leds four matched current sinks that control led backlighting current, with 0ma to 25ma per led two adjustable ldos with outputs ranging from 1.5v to 3.3v for ldo1 and 1.2v to 1.8v for ldo2, adjustable in 100mv increments high current fractional charge pump the backlight outputs are supported by a high e ciency, high current fractional charge pump output at the out pin. the charge pump multiplies the input voltage by 1, 1.5, or 2 times. the charge pump switches at a xed fre- quency of 250khz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve e ciency. the mode selection circuit automatically selects the mode as 1x, 1.5x, or 2x based on circuit conditions such as led voltage, input voltage, and load current. the 1x mode is the most e cient of the three modes, followed by 1.5x and 2x modes. circuit conditions such as low input voltage, high output current, or high led voltage place a higher demand on the charge pump output. a higher numerical mode (1.5x or 2x) may be needed momentarily to main- tain regulation at the out pin during intervals of high demand. the charge pump responds to momentary high demands, setting the charge pump to the optimum mode to deliver the output voltage and load current while opti- mizing e ciency. hysteresis is provided to prevent mode toggling. the charge pump requires two bucket capacitors for proper operation. one capacitor must be connected between the c1+ and c1- pins and the other must be con- nected between the c2+ and c2- pins as shown in the typical application circuit diagram. these capacitors should be equal in value, with a nominal capacitance of 1.0f to support the charge pump current requirements. ? ? ? note that small package capacitors can decrease in value by up to 50% under dc loading, so it is strongly recom- mended that 2.2uf capacitors be selected when using 0402 size ceramic capacitors. the device also requires a 2.2f capacitor on the in pin and a 2.2f capacitor on the out pin to minimize noise and support the output drive requirements. capacitors with x7r or x5r ceramic dielectric are strongly recommended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coe cients make them unsuitable for this application. led backlight current sinks the backlight current is set via the sempulse interface. the current is regulated to one of 29 values between 0ma and 25ma. the step size varies depending upon the current setting. the step sizes are 0.5ma for current set- tings between 0ma and 5ma. the step size increases to 1ma for settings between 5ma and 21ma. steps are 2ma between 21ma and 25ma. the variation in step size allows ner adjustment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in led brightness. a zero setting is also included to allow the current sink to be disabled by writing to either the enable bit or the current setting reg- ister for maximum exibility. all backlight current sinks have matched currents, even when there is variation in the forward voltages (v f ) of the leds. a v f of 1.2v is supported when the input voltage is at 3.0v. higher v f led mis-match is supported when v in is higher than 3.0v. all current sink outputs are compared and the lowest output is used for setting the voltage regulation at the out pin. this is done to ensure that su cient bias exists for all leds. the backlight leds default to the o state upon power- up. for backlight applications using less than four leds, any unused output must be left open and the unused led driver must remain disabled. when writing to the backlight enable register, a zero (0) must be written to the corresponding bit of any unused output. applications information
SC653 13 applications information (continued) backlight quiescent current the quiescent current required to operate all four back- lights is reduced by 1.5ma when backlight current is set to 4.0ma or less. this feature results in higher e ciency under light-load conditions. further reduction in quiescent current will result from using fewer than four leds. fade-in and fade-out the SC653 contains bits that control the fade state of the main bank. when enabled, the fade function causes the backlight settings to step from their current state to the next programmed state as soon as the new state is stored in its register. for example, if the backlight is set at 25ma and the next setting is the o state, the backlight will step from 25ma down to 0ma using all 29 settings at the fade rate speci ed by the bits in register 04h. the same is true when turning on or increasing the backlight current the backlight current will step from the present level to the new level at the step rate de ned in register 04h. this process applies for both the main and the sub displays. the fade rate may be changed dynamically when a fade operation is active by writing new values to the fade reg- ister. when a new backlight level is written during an ongoing fade operation, the fade will be redirected to the new value from the present state. an ongoing fade opera- tion may be cancelled by disabling fade which will result in the backlight current changing immediately to the nal value. if fade is disabled, the current level will change immediately without the fade delay. the state diagram in figure 1 describes all possible conditions for a fade opera- tion. more details can be found in the register map section. write fade=0 write new bright level fade=0 no change write fade=0 fade=1 fade processing (1) write new bright level write new bright level fade is redirected toward the new value from current state fade begins fade ends write fade=1 fade=1 fade=0 immediate change to new bright level fade=0 write fade=1 no change write fade=1 no change immediate change to new bright level write new fade rate continue fade using new rate note: (1) when the data in backlight enable register 01h is not 00h figure 1 fade state diagram programmable ldo outputs two low dropout (ldo) regulators are provided for camera module i/o and core power. each ldo output voltage setting has 3.5% accuracy over the operating temperature range. output current greater than the speci cation is possible at somewhat reduced accuracy. input pins enl1 and enl2 may be used to directly enable and disable the ldos without communication via the spif interface. when power is rst applied to the SC653, the register defaults reset the ldos to the o state, so spif must be used one time to set the voltages before enl1 and enl2 can be used to enable the ldos.
SC653 14 to control ldos exclusively by software, enl1 and enl2 may be permanently terminated to the battery voltage. enl1 must be high for the spif interface to control ldo1. when low, enl1 disables ldo1. enl2 is used exactly the same way to enable and disable ldo2. a 1f, low esr capacitor should be used as a bypass capacitor on each ldo output to reduce noise and ensure stability. in addition, it is recommended that a nominal minimum 22nf capacitor be connected between the byp pin and the gnd1 pin to minimize noise and achieve optimum power supply rejection. a larger capacitor can be used for this function, but at the expense of increasing turn-on time. capacitors with x7r or x5r ceramic dielec- tric are strongly recommended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coef- cients make them unsuitable for this application. shutdown mode the device is disabled when the spif pin is held low for the shutdown time speci ed in the electrical characteris- tics section. all registers are reset to default condition at shutdown. typical current consumption in this mode is 0.1a. sleep mode when all leds are disabled, sleep mode is activated. this is a reduced current mode that helps minimize overall current consumption by disabling the clock and the charge pump while continuing to monitor the serial interface for commands. the two ldos can be enabled when the device is in sleep mode. protection features the SC653 provides several protection features to safe- guard the device from catastrophic failures. these fea- tures include: output open circuit protection over-temperature protection charge pump output current limit ldo current limit led float detection ? ? ? ? ? applications information (continued) output open circuit protection over-voltage protection (ovp) is provided at the out pin to prevent the charge pump from producing an exces- sively high output voltage. in the event of an open circuit at out, the charge pump runs in open loop and the voltage rises up to the ovp limit. ovp operation is hyster- etic, meaning the charge pump will momentarily turn o until v out is sufficiently reduced. the maximum ovp threshold is 6.0v, allowing the use of a ceramic output capacitor rated at 6.3v. over-temperature protection the over-temperature (ot) protection circuit prevents the device from overheating and experiencing a catastrophic failure. when the junction temperature exceeds 165 c, the device goes into thermal shutdown with all outputs dis- abled until the junction temperature is reduced. all regis- ter information is retained during thermal shutdown. hysteresis of 30c is provided to ensure that the device cools su ciently before re-enabling. charge pump output current limit the device limits the charge pump current at the out pin. when out is shorted to ground, the output current will typically equal 250ma. the output current is also limited to 250ma when over-loaded resistively. ldo current limit the device limits the output currents of ldo1 and ldo2 to help prevent the device from overheating and to protect the loads. the minimum limit is 200ma, so load current greater than the rated current and up to 200ma can be used with degraded accuracy and larger dropout without tripping the current limit. led float detection float detect is a fault detection feature of the led current sink outputs. if an output is programmed to be enabled and an open circuit fault occurs at any current sink output, that output will be disabled to prevent a sustained output ovp condition from occurring due to the resulting open loop. float detect ensures device protection but does not ensure optimum performance. unused led outputs must be disabled to prevent an open circuit fault from occurring.
SC653 15 pcb layout considerations the layout diagram in figure 2 illustrates a proper two-layer pcb layout for the SC653 and supporting com- ponents. following fundamental layout rules is critical for achieving the performance specified in the electrical characteristics table. the following guidelines are recommended when developing a pcb layout: place all bucket, bypass, and decoupling capaci- tors c1, c2, cin, cout, cldo1, cldo2, and cbyp as close to the device as possible. all charge pump current passes through in, out, and the bucket capacitor connection pins. ensure that all connections to these pins make use of wide traces so that the resistive drop on each connection is minimized. the thermal pad should be connected to the ground plane using multiple vias to ensure proper thermal connection for optimal heat transfer. ? ? ? applications information (continued) the following capacitors cldo1, cldo2, and cbyp should be grounded together through an isolated copper island. using no vias, connect the island only, to pin 7 as shown in figure 2. figure 3 shows only the vias that should be con- nected to the ground plane with multiple vias. make all ground connections to a solid ground plane as shown in figure 4. all ldo output traces should be made as wide as possible to minimize resistive losses. ? ? ? ? tbd figure 4 layer 2 tbd figure 2 recommended pcb layout tbd figure 3 layer 1 c1 c2 out SC653 gnd2 1 2 3 4 56 7 89 13 12 11 10 14 15 16 17 18 cout island for pin 7 gnd1 (no vias) ground layer cbyp keep gap open vias to ground plane cldo2 cldo1 cin in figure 2 ? recommended pcb layout figure 3 ? layer 1 figure 4 ? layer 2
SC653 16 introduction sempulse is a write-only single wire interface. it provides access to up to 32 registers that control device functional- ity. two sets of pulse trains are transmitted via the spif pin. the rst pulse set is used to set the desired address. after the bus is held high for the address hold period, the next pulse set is used to write the data value. after the data pulses are transmitted, the bus is held high again for the data hold period to signify the data write is complete. at this point the device latches the data into the address that was selected by the first set of pulses. see the sempulse timing diagrams for descriptions of all timing parameters. chip enable/disable the device is enabled when the sempulse interface pin (spif) is pulled high for greater than t su . if the spif pin is pulled low again for more than t sd , the device will be disabled. address writes the rst set of pulses can range between 0 and 31 (or 1 to 32 rising edges) to set the desired address. after the pulses are transmitted, the spif pin must be held high for t holda to notify the slave device that the address write is nished. if the pulse count is between 0 and 31 and the line is held high for t holda , the address is latched as the destination for the data word. if the spif pin is not held high for t holda , the slave device will continue to count pulses. if the total exceeds 31 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. note that if t holda exceeds its maximum speci cation, the bus will reset. this means that the com- munication is ignored and the bus resumes monitoring the pin, expecting the next pulse set to be an address. data writes after the bus has been held high for the minimum address hold period, the next set of pulses are used to write the data value. the total number of pulses can range from 0 to 63 (or 1 to 64 rising edges) since there are a total of 6 register bits per register. just like with the address write, the data write is only accepted if the bus is held high for t holdd when the pulse train is completed. if the proper hold time is not received, the interface will keep counting pulses until the hold time is detected. if the total exceeds 63 pulses, the write will be ignored and the bus will reset after the next valid hold time is detected. after the bus has been held high for t holdd , the bus will expect the next pulse set to be an address write. note that this is the same e ect as the bus reset that occurs when t holda exceeds its maximum speci cation. for this reason, there is no maximum limit on t holdd the bus simply waits for the next valid address to be transmitted. multiple writes it is important to note that this single-wire interface requires the address to be paired with its corresponding data. if it is desired to write multiple times to the same address, the address must always be re-transmitted prior to the corresponding data. if it is only transmitted one time and followed by multiple data transmissions, every other block of data will be treated like a new address. the result will be invalid data writes to incorrect addresses. note that multiple writes only need to be separated by the minimum t holdd for the slave to interpret them cor- rectly. as long as t holda between the address pulse set and the data pulse set is less than its maximum speci cation but greater than its minimum, multiple pairs of address and data pulse counts can be made with no detrimental e ects. standby mode once data transfer is completed, the spif line must be returned to the high state for at least 10ms to return to the standby mode. in this mode, the spif line remains idle while monitoring for the next command. this mode allows the device to minimize current consumption between commands. once the device has returned to standby mode, the bus is automatically reset to expect the address pulses as the next data block. this safeguard is intended to reset the bus to a known state (waiting for the beginning of a write sequence) if the delay exceeds the reset threshold. sempulse ? interface
SC653 17 sempulse ? interface (continued) the sempulse single wire interface is used to enable or disable the device and con gure all registers (see figure 2). the timing parameters refer to the digital i/o electrical speci cations. t lo t hi t = t su t = t holda t = t holdd address is set data is written spif up to 32 rising edges (0 to 31 pulses) up to 64 rising edges (0 to 63 pulses) figure 2 uniform timing diagram for sempulse communication timing example 1 in this example (see figure 3), the slave chip receives a sequence of pulses to set the address and data, and the pulses experience interrupts that cause the pulse width to be non-uniform. note that as long as the maximum high and low times are satis ed and the hold times are within speci cation, the data transfer is completed regardless of the number of interrupts that delay the transmission. t hi t lo t < t himax t < t lomax t = t su data written is 000011 spif t = t holda t = t holdd address is set to register 02h figure 3 sempulse data write with non-uniform pulse widths timing example 2 in this example (see figure 4), the slave chip receives two sets of pulses to set the address and data, but an interrupt occurs during a pulse that causes it to exceed the minimum address hold time. the write is meant to be the value 03h in register 05h, but instead it is interpreted as the value 02h written to register 02h. the extended pulse that is delayed by the interrupt triggers a false address detection, causing the next pulse set to be interpreted as the data set. to avoid any problems with timing, make sure that all pulse widths comply with their timing requirements as outlined in this datasheet. data written is 000010 spif t > t himax t = t holdd address is set to register 02h interrupt duration t = t holda address is set to register 03h (address and data are now out of order) figure 4 faulty sempulse data write due to extended interrupt duration
SC653 18 register map (1) address d5 d4 d3 d2 d1 d0 reset value description 00h 0 (2) bl_4 bl_3 bl_2 bl_1 bl_0 00h backlight current 01h 0 (2) 0 (2) blen_4 blen_3 blen_2 blen_1 00h backlight enable 02h 0 (2) 0 (2) ldo1_3 ldo1_2 ldo1_1 ldo1_0 00h ldo1 03h 0 (2) 0 (2) 0 (2) ldo2_2 ldo2_1 ldo2_0 00h ldo2 04h 0 (2) 0 (2) 0 (2) fade_1 fade_0 fade_en 00h fade notes: (1) all registers are write-only. (2) 0 = always write a 0 to these bits de nition of registers and bits bl current control register (00h) this register is used to set the currents for the backlight current sinks. these current sinks need to be enabled in the backlight enable control register to be active. bl[d4:d0] these bits are used to set the current for the backlight current sinks. all enabled backlight current sinks will sink the same current, as shown in table 1. table 1 backlight current settings bl_4 bl_3 bl_2 bl_1 bl_0 backlight current (ma) 0000 0 0 0 0 0 0 1 see note 1 0 0 0 1 0 see note 1 0 0 0 1 1 see note 1 0 0 1 0 0 0.5 0010 1 1 0 0 1 1 0 1.5 0011 1 2 0 1 0 0 0 2.5 0100 1 3 0 1 0 1 0 3.5 bl_4 bl_3 bl_2 bl_1 bl_0 backlight current (ma) 0101 1 4 0 1 1 0 0 4.5 0110 1 5 0111 0 6 0111 1 7 1000 0 8 1000 1 9 1001 0 10 1001 1 11 1010 0 12 1010 1 13 1011 0 14 1011 1 15 1100 0 16 1100 1 17 1101 0 18 1101 1 19 1110 0 20 1110 1 21 1111 0 23 1111 1 25 (1) reserved for future use
SC653 19 register and bit de nitions (continued) backlight enable control register (01h) this register is used to enable the backlight current sinks. blen[d4:d1] these bits are used to enable current sinks (active high, default low). blen_4 enable bit for backlight bl4 blen_3 enable bit for backlight bl3 blen_2 enable bit for backlight bl2 blen_1 enable bit for backlight bl1 when enabled, the current sinks will carry the current set by the backlight current control bits bl[4:0], as shown in table 1. ldo1 control register (02h) this register is used to enable ldo1 and set the output voltage v ldo1 . ldo1[d3:d0] these bits set the output voltage, v ldo1 , as shown in table 2. table 2 ldo1 control bit s ldo1_3 ldo1_2 ldo1_1 ldo1_0 v ldo1 0000 off 0001 3.3v 0010 3.2v 0011 3.1v 0100 3.0v 0101 2.9v 0110 2.8v 0111 2.7v 1000 2.6v 1001 2.5v 1010 2.4v 1011 2.2v 1100 1.8v 1101 1.7v 1110 1.6v 1111 1.5v ldo2 control register (03h) this register is used to enable the ldo2 and to set the output voltage v ldo2 . ldo2[d2:d0] these bits are used to set the output voltage, v ldo2 , as shown in table 3. table 3 ldo2 control bits ldo2_2 ldo2_1 ldo2_0 v ldo2 0 0 0 off 0 0 1 1.8v 0 1 0 1.7v 0 1 1 1.6v 1 0 0 1.5v 1 0 1 1.4v 1 1 0 1.3v 1 1 1 1.2v fade control register (04h) this register is used to enable the backlight fade and to set the rise and fall rate at which fading proceeds. fade[d2:d1] these bits are used to set the rise/fall rate between two backlight currents as shown in table 4. table 4 fade control bits fade_1 fade_0 fade feature rise/fall rate (ms/step) 0 0 32 01 24 10 16 11 8 the number of steps in changing the backlight current will be equal to the change in binary count of bits bl[4:0].
SC653 20 fade_en [d0] this bit is used to enable or disable the fade feature. when the fade function is enabled and a new backlight current is set, the backlight current will change from its current value to a new value set by bits bl[4:0] at a rate of 8ms to 32ms per step. a new backlight level cannot be written during an ongoing fade operation, but an ongoing fade operation may be cancelled by resetting the fade bit. clearing the fade bit during an ongoing fade operation changes the backlight current immediately to the value of bl[4:0]. the number of counts to complete a fade opera- tion equals the difference between the old and new backlight values to increment or decrement the bl[4:0] bits. if the fade bit is cleared, the current level will change immediately without the fade delay. the rate of fade may be changed dynamically, even while a fade operation is active, by writing new values to the fade_1 and fade_0 bits. the total fade time is determined by the number of steps between old and new backlight values, multiplied by the rate of fade in ms/step. the longest elapsed time for a full scale fade-out of the backlight is nominally 938ms when the default interval of 32ms is used. register and bit de nitions (continued)
SC653 21 2.30 2.20 2.40 notes: 0.08 18 1.15 0.00 0.50 1.25 1.20 0.05 0.60 (0.152) - - 0.10 2.20 2.30 2.40 0.40 bsc 0.25 0.30 0.35 coplanarity applies to the exposed pad as well as the terminals. 2. controlling dimensions are in millimeters (angles in degrees). 1. dimensions e bbb aaa a1 a2 d1 e1 dim n l e d a millimeters max min nom 1 2 n pin 1 indicator (laser mark) seating plane b 0.15 0.20 0.25 e/2 e d/2 lxn e/2 bxn bbb c a b a b d e a1 aaa c a a2 c e1 1.15 1.20 1.25 d1 outline drawing mlpq-ut-18 2.3x2.3
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC653 22 land pattern mlpq-ut-18 2.3x2.3 this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 2. c z p y x k h 2.90 0.20 0.57 0.40 1.20 1.20 dim (2.33) millimeters dimensions failure to do so may compromise the thermal and/or thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. functional performance of the device. 3. controlling dimensions are in millimeters (angles in degrees). square package-dimensions apply in both x and y directions. 4. 1. g1.76 y g z (c) p x r r0.10 k h

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